News

Contacts:
David Hart, SDSC, 858-534-8314, 858-534-5113 (fax), dhart@sdsc.edu

UNIVERSITY OF CALIFORNIA, SAN DIEGO - The San Diego Supercomputer Center (SDSC) has announced its acceptance of an eight-processor Multithreaded Architecture (MTA) supercomputer built by Tera Computer Company of Seattle, Washington. The Tera MTA, with eight processors and eight gigabytes of shared memory, was delivered to SDSC several weeks ago and now has passed the full suite of acceptance tests.

"A workshop here in May showed encouraging progress in implementing scientific and engineering applications on the four-processor MTA," said Wayne Pfeiffer, Deputy Director for Technology at SDSC. Participating were researchers from several institutions evaluating the Tera system at SDSC with funding from NSF, DARPA, and DOE. "Subsequent tests on some of the applications have demonstrated good scalability to eight MTA processors and absolute performance comparable to that on other supercomputers at SDSC," Pfeiffer said.

Scalability refers to the performance improvement of a computer system as more processors are added, with linear scalability being ideal. A unique feature of the MTA is its ability to scale from one to many processors with no change in the programming model. Two of the applications that have shown good scalability are PULSE3D and MPIRE.

PULSE3D is a heart simulation code developed by Charles Peskin and David McQueen of the Courant Institute at New York University and ported to the MTA by SDSC's Rich Charles and Tera personnel. (See http://www.cat.nyu.edu/projects/virtualheart.html.) "PULSE3D simulates in three dimensions the beating of a human heart," said Charles, a mechanical engineer specializing in computational fluid dynamics and scientific visualization.

The coupled fluid/structure simulation done by PULSE3D is extremely demanding computationally and a major consumer of cycles on SDSC's traditional vector supercomputer. "Currently it takes about ten days on a single vector processor to simulate one heartbeat," said Charles.

"PULSE3D now runs as fast on eight MTA processors as on eight vector processors and scales better on the MTA," Charles noted. "The good scaling means that more accurate, higher resolution simulations could be done if the MTA were upgraded to more processors."

According to Charles, the MTA is well suited for handling fluid/structure interaction problems, which are most efficiently solved by a computer that has a large shared memory to keep track of the fluid domain and multiple processors to model movement of the structure. "In some portions of PULSE3D the good match between computer architecture and problem type has resulted in simpler, faster code on the MTA," Charles said.

The MPIRE system was developed by SDSC computer scientists Jon Genetti, Greg Johnson, and Allan Snavely to visualize volume data from medical, astronomical, and other sources. (See http://mpire.sdsc.edu/.) "Porting MPIRE to the MTA was simplicity itself," said Snavely. "This effort really showed the elegance of Tera's programming model compared to that used on other parallel computers."

One of the components of MPIRE, the MPIRE Raycaster, is used primarily for visualizing data from the Visible Human Project at the National Library of Medicine ( http://www.nlm.nih.gov/research/visible/). According to Johnson, "the MPIRE Raycaster scales extremely well on the MTA, and runs faster on eight MTA processors than on 64 processors of the distributed-memory supercomputers at SDSC."

A second component, the MPIRE Galaxy Renderer, is being used to visualize nebula-like structures in interstellar space. These tenuous, translucent formations of dust and gas are difficult to visualize realistically with traditional computer graphics techniques. "Using Galaxy Renderer, we can create visualizations of nebular structures that match our natural view of the world more closely than other graphics codes allow," said Johnson. "Performance of the Galaxy Renderer on the MTA is excellent, with parallel efficiency of 99% up to eight processors. Needless to say, we are happy with these results."

The Tera MTA at SDSC has been upgraded to larger configurations in stages -first a single processor, then two, then four, and now eight processors - through addition of production circuit boards and other components. A four-processor MTA was first demonstrated at the beginning of 1999.

For more information about Tera and its MTA systems, see http://www.tera.com/, or contact Tera Computer Company, 206-701-2000 (voice), 206-701-2500 (fax), info@tera.com, 411 First Avenue South, Suite 600, Seattle, WA 98104-2860.The San Diego Supercomputer Center is a research unit of the University of California, San Diego, and the leading-edge site of the National Partnership for Advanced Computational Infrastructure ( http://www.npaci.edu/). SDSC is sponsored by the National Science Foundation through NPACI and by other federal agencies, the State and University of California, and private organizations. For additional information about SDSC, see http://www.sdsc.edu/, or contact David Hart at 858-534-8314, dhart@sdsc.edu.